`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    02:34:21 02/24/2012 
// Design Name: 
// Module Name:    pcie_axi_bridge 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module pcie_axi_bridge(
  input           CLK,
  input           RST,
  
  input           S_TVALID,
  output          S_TREADY,
  input   [127:0] S_TDATA,
  input   [3:0]   S_TSTRB,
  input           S_TLAST,
  output          M_TVALID,
  input           M_TREADY,
  output  [127:0] M_TDATA,
  output  [3:0]   M_TSTRB,
  output          M_TLAST,
  
  input   [31:0]  S_AWADDR,
  input           S_AWVALID,
  output          S_AWREADY,
  input   [31:0]  S_WDATA,
  input   [3:0]   S_WSTRB,
  input           S_WVALID,
  output          S_WREADY,
  output  [1:0]   S_BRESP,
  output          S_BVALID,
  input           S_BREADY,
  input   [31:0]  S_ARADDR,
  input           S_ARVALID,
  output          S_ARREADY,
  output  [31:0]  S_RDATA,
  output  [1:0]   S_RRESP,
  output          S_RVALID,
  input           S_RREADY,

  input   [31:0]  S0_AWADDR,
  input   [7:0]   S0_AWLEN,
  input           S0_AWVALID,
  output          S0_AWREADY,
  input   [31:0]  S0_WDATA,
  input   [3:0]   S0_WSTRB,
  input           S0_WVALID,
  output          S0_WREADY,
  output  [1:0]   S0_BRESP,
  output          S0_BVALID,
  input           S0_BREADY,
  input   [31:0]  S0_ARADDR,
  input   [7:0]   S0_ARLEN,
  input           S0_ARVALID,
  output          S0_ARREADY,
  output  [31:0]  S0_RDATA,
  output  [1:0]   S0_RRESP,
  output          S0_RVALID,
  input           S0_RREADY,

  output  [31:0]  M0_AWADDR,
  output  [7:0]   M0_AWLEN,
  output          M0_AWVALID,
  input           M0_AWREADY,
  output  [31:0]  M0_WDATA,
  output  [3:0]   M0_WSTRB,
  output          M0_WLAST,
  output          M0_WVALID,
  input           M0_WREADY,
  input   [1:0]   M0_BRESP,
  input           M0_BVALID,
  output          M0_BREADY,
  output  [31:0]  M0_ARADDR,
  output  [7:0]   M0_ARLEN,
  output          M0_ARVALID,
  input           M0_ARREADY,
  input   [31:0]  M0_RDATA,
  input           M0_RLAST,
  input   [1:0]   M0_RRESP,
  input           M0_RVALID,
  output          M0_RREADY
  );
  assign S_TREADY = 1'b0;
  assign S_AWREADY = 1'b0;
  assign S_WREADY = 1'b0;
  assign S_BRESP = 2'b0;
  assign S_BVALID = 1'b0;
  assign S_ARREADY = 1'b0;
  assign S_RDATA = 32'b0;
  assign S_RRESP = 2'b0;
  assign S_RVALID = 1'b0;

/*
  SlaveBridge sb(
    .CLK(),
    .RST(),
    
    .S_TVALID(),
    .S_TREADY(),
    .S_TDATA(),
    .S_TSTRB(),
    .S_TLAST(),
    .M_TVALID(),
    .M_TREADY(),
    .M_TDATA(),
    .M_TSTRB(),
    .M_TLAST(),
  
    .S_AXI_AWADDR(),
    .S_AXI_AWVALID(),
    .S_AXI_AWREADY(),
    .S_AXI_WDATA(),
    .S_AXI_WSTRB(),
    .S_AXI_WVALID(),
    .S_AXI_WREADY(),
    .S_AXI_BRESP(),
    .S_AXI_BVALID(),
    .S_AXI_BREADY(),
    .S_AXI_ARADDR(),
    .S_AXI_ARVALID(),
    .S_AXI_ARREADY(),
    .S_AXI_RDATA(),
    .S_AXI_RRESP(),
    .S_AXI_RVALID(),
    .S_AXI_RREADY()
  );
  MasterBridge mb(
    .CLK(),
    .RST(),
    
    .S_TVALID(),
    .S_TREADY(),
    .S_TDATA(),
    .S_TSTRB(),
    .S_TLAST(),
    .M_TVALID(),
    .M_TREADY(),
    .M_TDATA(),
    .M_TSTRB(),
    .M_TLAST(),
  
    .M_AXI_AWADDR(),
    .M_AXI_AWVALID(),
    .M_AXI_AWREADY(),
    .M_AXI_WDATA(),
    .M_AXI_WSTRB(),
    .M_AXI_WVALID(),
    .M_AXI_WREADY(),
    .M_AXI_BRESP(),
    .M_AXI_BVALID(),
    .M_AXI_BREADY(),
    .M_AXI_ARADDR(),
    .M_AXI_ARVALID(),
    .M_AXI_ARREADY(),
    .M_AXI_RDATA(),
    .M_AXI_RRESP(),
    .M_AXI_RVALID(),
    .M_AXI_RREADY()
  );
*/
endmodule
